CAREERS

Join our team

Everything we do is designed to challenge the limits of imaging and sensing technologies. We thrive on excellence in execution while having fun pushing the boundaries of what an image can express. We offer a permanent contract with a competitive salary and career opportunity in a growing company with global coverage and ambition. There’s still a lot of work to be done. We need best in class optical designers, software, parallel computing, heterogeneous computing and digital image processing experts. We’d like to hear from you If you have experience or a PhD in one of the following fields: Computer Science, Telecommunication Engineering, Parallel Computing, Electronic Engineering, Physics, Mathematics .

Candidates for available positions should send a Resume including relevant experience and a copy of academic results (Expediente Académico) to [email protected] indicating in the subject the email the title of job offer.

Senior ASIC Design & Verification Engineer

Experienced Microelectronics design and verification engineer to develop an innovative low-power consumption ASIC to deliver high-quality depth maps and images by processing real-time video frames captured by apiCAM, our leading state-of the art 3D camera.

apiCAM offers simultaneously 2D and 3D images with a single lens, currently at 30 fps (frames per second), higher in the future. apiCAM is available in commercial products for Medical Imaging, Robotics, Industry 4.0 and aims to be in the next generations of XR-glasses, Tablets, PCs and Smartphones.

You will join the our Algorithms team to improve and implement state-of-the-art depth and imaging algorithms efficiently on FPGAs and finally within an ASIC. This Team is part of our R&D Department with experts in Physical-Optics, Image-Processing, Algorithms, Software and Industrial Automation.

Responsibilities

Integration and Formal Verification of a complex digital design composed by multiple HDL-blocks developed by members of our Digital Design and Verification Groups as well as IP-blocks from third parties.
Porting our current algorithms to an ASIC.
Definition of the hardware-software architecture that guarantees the lowest power consumption, as well as maximum speed and precision in the calculations.
Development of the hardware system using Xilinx development tools for FPGAs.
RTL coding, simulation and verification.
Choice of the target digital process. RTL porting to the targeted ASIC-process.
Development of the control software for our camera.
C/C++ developments for embedded microprocessors (within FPGAs and ASICs).
Development of techniques to reduce computational costs.

Requirements

Bachelor, Master or PhD in Telecommunication, Electronics, Computer Science or related fields.
5+ years’ experience working on the design of complex FPGA and ASIC systems.
Experience in RISC-V and/or ARM embedded architectures.
Extensive experience in HDLs-Hardware Description Languages (Verilog and/or VHDL). Ability to integrate third party IPs.
Development of testbenches for the verification of digital designs (Verilog, SystemVerilog, UVM…).
Version control software such as Git or SVN.
Signal processing in software such as Matlab, Python and/or C++.
Analysis of complex algorithms and problems to find creative and innovative solutions.
Experience manufacturing digital-ASICs in silicon.
Motivated, and willing to take a leading role within a highly motivated design team and to face big challenges such as the design, verification, and manufacturing of a complex image processing ASIC from the very beginning.

Desirable

High-Performance Computing (HPC) and low-power consumption architectures for consumer appliances.
Knowledge of MIPI, USB 3.0, Ethernet and other camera-related communication protocols.
Knowledge of HLS (High-Level Synthesis) design using Vivado.
Knowledge of Image acquisition, 3D-scanning and Computer Vision paradigms: Stereo-vision, Structure from Motion (SfM), SLAM (Simultaneous Localization and Mapping), …
Knowledge of open source libraries: OpenCV, Open3D, Point Cloud Library,…

We offer

Competitive salary according to your experience.
Flexible working hours (1 teleworking day per week).
Flexible compensation plan (restaurant tickets, transport, childcare, health insurance…).
Professional career plan within the company. Lifelong learning.
Dynamic start-up environment.
Fix contract and professional stability within a demanding but friendly working environment.

Join us!

We create disruptive technologies! Weenjoy what we do and aim for global leadership in our disciplines. We live innovation every day, and we invite you to explore the opportunities offered. Come and discover it!

Send your Resume and copy of your Academic Results (Expediente Académico) to [email protected]

Digital Design Verification Engineer

Digital Design Verification Engineer to help developing an innovative low-power consumption ASIC to obtain high-quality depth maps and images by processing real-time video frames captured by apiCAM, our leading, state-of the-art 3D camera.

apiCAM offers simultaneously 2D and 3D with a single lens, currently at 30 fps (frames per second), higher in the future. apiCAM is already available in commercial products for Medical Imaging, Robotics, Industry 4.0 and aims to be in the next generation of XR-glasses, Tablets, PCs and Smartphones.

You will join our Algorithms team, specifically the Digital Verification Group for our state-of-the-art depth and imaging algorithms. This team is part of our R&D Department with experts in Physical-Optics, Image-Processing, Algorithms, Software and Industrial Automation.

Responsibilities

Contribute to the tasks defining low power consumption but extremely efficient digital designs.
Implement testbenches to ensure that the digital designs comply to specifications are robust and interact correctly with other IP-blocks. Will use Xilinx development tools for FPGAs and in the future Formal Verification tools for ASICs.
Collaborate with digital design engineers to redefine and optimize digital IP-blocks.

Requirements

Bachelor and/or Master degree in Telecommunication, Electronics, computer science or related fields.
HDL-Hardware Description Languages (Verilog or VHDL) and integration of IP-blocks. Development of testbenches using SystemVerilog and UVM methodologies for the verification of complex digital designs.
Version control software such as Git or SVN.
Understanding of signal processing algorithms in Matlab Python and/or C++.
Motivated, willing to work in a team and to face big challenges such as the design, verification, and manufacturing of a complex ASIC from the very beginning.

Desirable

Knowledge of basic FPGA architectures and modes of operation.
State machines.
Design of parametric testbenches and test vectors for complex digital designs.
Finite precision modelling in Matlab or others.

We offer

Competitive salary according to your experience.
Flexible working hours (1-2 teleworking days per week).
Flexible compensation plan (restaurant tickets, transport, childcare, health insurance…).
Professional career plan within the company. Lifelong learning.
Dynamic start-up environment.
Fix contract and professional stability within a demanding but friendly working environment.

Join us!

We create disruptive technologies, we aim for global leadership in our disciplines, we enjoy what we do, we live innovation every day, and we invite you to explore the opportunities offered. Come and discover it!

Send your Resume and copy of your Academic Results (Expediente Académico) to [email protected]

FPGA Digital Design Engineer

FPGA Digital Design Engineer required to join our team developing an innovative low-power consumption ASIC to obtain high-quality depth maps and images by processing real-time video frames captured by apiCAM, our leading, state-of the-art 3D camera.

You will join our Algorithms team, specifically the group porting our state-of-the-art depth and imaging algorithms to FPGAs and finally to an ASIC. This team is part of our R&D Department with experts in Physical-Optics, Image-Processing, Algorithms, Software and Industrial Automation.

Responsibilities

Porting blocks of our current algorithms to FPGAs.
Development of digital image and depth computation IP-blocks using Xilinx tools for FPGAs.
Analysis, design, and integration of low power consumption but the most efficient possible digital designs for real-time depth mapping.
Collaborate with other members of the Digital Design and Verification Engineering Groups to jointly redefine and optimize complete designs including multiple IP-blocks.

Knowledge Requirements

Bachelor and/or Master degree in Telecommunication, Electronics, Computer Science or related fields.
HDLs-Hardware Description Languages (Verilog and/or VHDL) and integration of IP-blocks.
Version control software such as Git or SVN.
Ability to understand signal processing algorithms in software such as Matlab, Python and/or C++.
Motivated, willing to work in a team and to face big challenges such as the design, verification, and manufacturing of an ASIC from the very beginning.

Desirable Experience

Knowledge of basic FPGA architectures, operation modes (sequential, parallel or hybrid).
State machines.
Finite precision modelling in Matlab or others.

We offer

Competitive salary according to your experience.
Flexible working hours (1-2 teleworking days per week).
Flexible compensation plan (restaurant tickets, transport, childcare, health insurance…).
Professional career plan within the company. Lifelong learning.
Dynamic start-up environment.
Fix contract and professional stability within a demanding but friendly working environment.

Join us!

We create disruptive technologies. We enjoy what we do and aim for global leadership in our disciplines. We live innovation every day, and we invite you to explore the opportunities offered. Come and discover your capabilities!

Send your Resume and copy of your Academic Results (Expediente Académico) to [email protected]